using System;
using System.Collections.Generic;
using System.Text;

namespace RapidHDL
{
    public class Settings
    {
        public int ClockFrequency;
        public string OutputPath;
        public string InterfaceSourcePath;
        public string XilinxToolsPath;
        public string XilinxChip;
        public bool OptimizeSpeed;
        public bool UseClock;
        public bool UseReset;
        public bool UseStart;
        public string TopComponentName;
        public bool DisableCheckWellFormed;

        public bool UseSDRAM;
        public int SDRAMDataBits;
        public int SDRAMAddressBits;
        public int SDRAMBankBits;
        public int SDRAMMaskBits;

        public bool UseFIFO;

        public bool BuildHardware;
        public bool RunFromXilinx;
        public bool ForceBuildHardware;

        public bool UseTestBus;

        public bool BuildRemote;
        public string BuildServerPath;

        public bool SkipVerilogGeneration;

        public bool SynthASIC;
        public string SynthLibaray;

        public bool SimulateVerilog;
        public string IcarusPath;
        public string LeonardoPath;
        public int ClockPeriodNs;

        public StructureTransformType OutputFormat;

        public string RemoteFPGAServer;
        
        public Settings()
        {
            ClockFrequency = 1;
            OutputPath = "c:\\src\\rapidhdl\\rhdl_out";
            //InterfaceSourcePath = "c:\\hdl\\pico";
            InterfaceSourcePath = "c:\\src\\rapidhdl\\extras\\hdl\\pico";
            XilinxToolsPath = "c:\\Xilinx\\10.1\\ISE\\bin\\nt";
            XilinxChip = "xc4vlx25-sf363-12";
            //XilinxChip = "xc4vfx12-sf363-12";
            UseClock = true;
            UseReset = true;
            UseStart = true;
            UseSDRAM = false;
            UseFIFO = false;
            SynthASIC = false;
            SynthLibaray = "tsmc035_typ";
            OptimizeSpeed = true;
            BuildHardware = false;
            RunFromXilinx = false;
            TopComponentName = "CFBase";
            OutputFormat = StructureTransformType.Verilog;
            ForceBuildHardware = false;
            SDRAMDataBits = 32;
            SDRAMAddressBits = 24;
            SDRAMBankBits = 4;
            SDRAMMaskBits = 2;
            BuildRemote = false;
            DisableCheckWellFormed = false;
            BuildServerPath = "xilinx.hopto.org:8080";
            SkipVerilogGeneration = false;
            UseTestBus = false;
            SimulateVerilog = false;
            IcarusPath = "c:\\src\\rapidhdl\\icarus\\bin";
            LeonardoPath = @"C:\MGC\LeoSpec\LS2008b_3\bin\win32\";
            ClockPeriodNs = 100;
            RemoteFPGAServer = "";
        }

        public void Normalize()
        {
            OutputPath = Utility.NormalizePath(OutputPath);
            InterfaceSourcePath = Utility.NormalizePath(InterfaceSourcePath);
            XilinxToolsPath = Utility.NormalizePath(XilinxToolsPath);
            IcarusPath = Utility.NormalizePath(IcarusPath);
            LeonardoPath = Utility.NormalizePath(LeonardoPath);            
        }

        public void CopySettings(Settings poSettings)
        {
            OutputPath = poSettings.OutputPath;
            InterfaceSourcePath = poSettings.InterfaceSourcePath;
            XilinxToolsPath = poSettings.XilinxToolsPath;
            XilinxChip = poSettings.XilinxChip;
            UseClock = poSettings.UseClock;
            UseReset = poSettings.UseReset;
            UseStart = poSettings.UseStart;
            UseSDRAM = poSettings.UseSDRAM;
            UseFIFO = poSettings.UseFIFO;
            OptimizeSpeed = poSettings.OptimizeSpeed;
            BuildHardware = poSettings.BuildHardware;
            RunFromXilinx = poSettings.RunFromXilinx;
            TopComponentName = poSettings.TopComponentName;
            OutputFormat = poSettings.OutputFormat;
            ForceBuildHardware = poSettings.ForceBuildHardware;
            SDRAMDataBits = poSettings.SDRAMDataBits;
            SDRAMAddressBits = poSettings.SDRAMAddressBits;
            SDRAMBankBits = poSettings.SDRAMBankBits;
            SDRAMMaskBits = poSettings.SDRAMMaskBits;
            BuildRemote = poSettings.BuildRemote;
            DisableCheckWellFormed = poSettings.DisableCheckWellFormed;
            BuildServerPath = poSettings.BuildServerPath;
            SkipVerilogGeneration = poSettings.SkipVerilogGeneration;
            UseTestBus = poSettings.UseTestBus;
            SynthASIC = poSettings.SynthASIC;
            SynthLibaray = poSettings.SynthLibaray;
            SimulateVerilog = poSettings.SimulateVerilog;
            IcarusPath = poSettings.IcarusPath;
            LeonardoPath = poSettings.LeonardoPath;
            ClockPeriodNs = poSettings.ClockPeriodNs;
            RemoteFPGAServer = poSettings.RemoteFPGAServer;
        }

    }


}
